The present disclosure relates generally to semiconductor integrated circuits (ICs). More particularly, the present disclosure relates to methods and structures including lines and vias as used in integrated circuits (ICs).
In order to be able to make integrated circuits (ICs), such as memory, logic, and other devices, of higher integration density than currently feasible, one has to find ways to further downscale the dimensions of field effect transistors (FETs), such as MOSFETs, and complementary metal oxide semiconductors (CMOS), and of similarly-scaled conductive wiring between them. Scaling achieves compactness and improves operating performance in devices by shrinking the overall dimensions and operating voltages of the device while maintaining the device's electrical properties.
Increased scaling can provide some difficulties with forming small-pitch metal wiring and the necessary interlevel vias. Typically, self aligned processes are employed for forming the wiring and vias to the device, in which metal troughs for the lines are defined in an interlevel dielectric mask or in a hard mask, and the vias are printed and etched in such a way that only the union of the metal trough and the via shape form vias down to the underlying metal layer. Reliable printing of vias can be problematic for aggressively scaled devices, so vias having a bar shape may be employed to increase pattern printability. Typically, a via opening is formed where the via bar shape crosses the union with the metal trough for the metal line. However, if the bar overlaps onto an adjacent metal trough than the union can result in an undesirable via that could short the lines formed in the metal trough that are interconnected by the undesirable via.